The present invention relates to the field of electronic circuits, and, more particularly, to memory devices. More specifically, the invention relates to a high bit density, high speed, via and metal BE type programmable read only memory (ROM) core cell architecture for storing of large amounts of non-volatile data which provides a relatively fast turn around time.
The complexity of integrated circuits is continually increasing. As a result, there is need for high bit density ROMs that can store large amounts of non-volatile data and that allow quick access thereto. In today""s competitive market, the time to market an electronic device needs to be as short as possible. Thus, when ROMs are used in such electronic devices, the ROMs should provide for a short turn around time. The turn around time primarily depends upon the fabrication stage at which programming of non-volatile data is done. If the programming is done at a later stage of fabrication, turn around time will be less.
Depending upon the level of programmability, ROMs are classified into two categories, namely, FE (lower levels, like active/poly/oxides/doping) and BE (metal/via/contact) programmable. FE programmable ROMS have high bit density, but they also have a longer turn around time. On the other hand, BE programmable ROMs have a fast turn around time, but they have reduced bit density. Thus, there is a need for a high density ROM that has fast turn around time.
Conventional ROM memory cells may include a transistor for storing each bit of information. The memory cells are organized on a row-and-column basis. The core matrix of a via programmable ROM cell is shown in FIG. 1. It has a bit line BL running xe2x80x9cverticallyxe2x80x9d and a word line WL running xe2x80x9chorizontally.xe2x80x9d A MOS transistor T00 stores one bit of data, i.e. a 0 or 1. The source of the transistor T00 is connected to GND (e.g., a ground supply line), and its gate is connected to the word line WL. Node 1, which is connected to the drain of the transistor T00, allows for programing by a via connected to the bit line BL.
The drain is programmed through the bit line BL and via to store one bit of data. Initially, the bit line BL is pre-charged to a voltage on a power supply line (e.g., VDD). When the memory cell is accessed by enabling one particular word line WL, if the via is present to connect the drain of memory cell transistor to the bit line, the bit line will discharge through the transistor to ground. One of these two conditions is understood as 0 and the other as 1.
The layout of a conventional BE programmable ROM in 0.18 micron technology is shown in FIG. 2. The bit line is a metallization layer (metal3), and the ground GND is formed by diffusion. Programming is performed using via2. From FIG. 2 it is clear that since contacts can not be shared between vertically adjacent memory cells, more surface area is required. Though a conventional BE programmable ROM has the advantage of fast time to market, it may suffer from the following disadvantages: the area of a BE programmable ROM memory cell is 30%-40% more than that of an FE programmable ROM memory cell; the transistor size is fixed and determined by contact size and related design rules; the GND is formed by diffusion, which increases the resistance of an access transistor and hence reduces the speed; and reliability is reduced since the drains of the unprogrammed cells are at a high impedance.
Based on the foregoing background, it is an object of the present invention to provide a high bit density in a BE programmable ROM core cell architecture.
Another object of the invention is to provide a memory cell transistor size that is larger than a contact size to provide increased speed.
Yet another object of the present invention is to provide a method of programming in which no node in the memory cell is in a high impedance state.
These and other objects, features, and advantages in accordance with the present invention are provided by a high bit density, high speed, via and metal BE type programmable ROM core cell architecture for storing large amounts of non-volatile data and having a relatively fast turn around time. The ROM core cell may include memory cells organized on a row and column basis where each of the memory cells includes three transistors and two bit lines. The arrangement between the three transistors and the two bit lines may be such that each of the memory cells is capable of storing four bits of data.
More particularly, the transistors may be MOS transistors. Any two of the three transistors may be capable of storing one bit of data in their respective drains and another bit of data in their respective sources independent of each other. During reading of the ROM, the capacitance of only selected bit lines is charged and all other bit lines are held at ground, which results in reduced power consumption and reduced leakage current.
The ground layer of the ROM may be routed in metal instead of being a diffusion layer, which provides less ground resistance. Moreover, the memory cell need not have any high impedance node, which provides improved reliability. Programming of the ROM may be performed using BE layers to achieve faster turn around timing. More particularly, programming of the transistors may be performed using 16 possible combinations, namely, xe2x80x9c0000xe2x80x9d, xe2x80x9c0001xe2x80x9d, xe2x80x9c0010, xe2x80x9c0011xe2x80x9d, xe2x80x9c0100xe2x80x9d, 0101xe2x80x9d, 0110, xe2x80x9c0111xe2x80x9d, xe2x80x9c1000xe2x80x9d, 1001, xe2x80x9c1010xe2x80x9d, xe2x80x9c1011xe2x80x9d, xe2x80x9c1100xe2x80x9d, xe2x80x9c1101, xe2x80x9c1110xe2x80x9d, xe2x80x9c1111xe2x80x9d.
Each memory cell may have two metal bit lines. The drain and source of each transistor in the memory cell may be connected to one metallization level in the memory cell. Thus, programming of the drain and source of the transistor may be performed by the bit line in same level metal, since the drain and source have a direct metal connection therewith, and also by connection to another bit line in a higher metallization level using a via.
The selected bit line is preferably of a memory cell that is going to be selected by the word line in the same cycle. This is achieved by proper designing of the row and column decoder of the ROM memory core. A logic 0 can be stored by connecting the drain of the transistor to one bit line and the source of the transistor to GND. A logic 0 may also be stored by connecting the drain of the transistor to one bit line and the source of the transistor to another bit line. Further, a logic 1 can be stored by connecting the drain and source of the transistor to the same bit line, or by connecting the drain and source of the transistor to GND.